1. Field of the Invention
The present invention relates to data transmission systems and, in particular, to circuitry for recovering a clock and binary data from a Manchester-encoded input using digital sampling.
2. Discussion of the Prior Art
Manchester encoding is a very popular means for transmitting a serial data stream for reception without including a separate clock signal. The clock is included with the data since, in accordance with Manchester encoding format, each bit cell must have a level transition in the middle of the bit cell (this transition will henceforth be referred to as a "midbit" transition). The midbit transition allows the receiver to remain synchronized to the incoming data by extracting a clock synchronized to the incoming data.
To maintain accurate decoding of received data, the noise on the transmission media must be distinguished from real data; this must be done in a manner such that data is not lost. To synchronize to a received frame, a unique pattern is sent to allow the receiver to properly align itself to the frame and to extract the binary data encoded in the pattern. The input to the receiver circuit must be a digital signal. Since the Manchester-encoded data is typically transmitted in a differential manner, a comparator typically precedes the receiver logic to perform this conversion.
Once the receiver logic is aligned to the incoming data, it extracts the binary data from the Manchester-encoded input by sampling the data at the appropriate point in time. As stated above, the sampling point is determined by generating a clock derived from the incoming data. Finally, upon reaching the end of a transmission, a unique pattern is typically sent to tell the receiver logic that the frame is ending and to wait for another starting pattern before extracting any more data.
One type of known receiver, the National Semiconductor Corporation DP8341 Serial Bi-Phase Receiver/Decoder, samples Manchester-encoded data at a frequency which is eight times greater than the data bit cell rate. The NSC DP8341 also provides a two bit divider for recovering the synchronized data sampling clock. The data sampling clock is then utilized to extract the binary data from the sampled data by sampling each half bit time of the sampled data bit cells.